1. Field of the Invention
The present invention relates to a semiconductor device and a method of detecting abnormality on a semiconductor device, and more particularly relates to a test for a word line and a word line driver in a memory cell array in a semiconductor device.
2. Description of Related Art
A method is known for testing a memory cell array in a semiconductor device (e.g.: a memory, a memory embedded microcomputer) having a memory circuit. Typically, a test method checks whether or not reading from and writing to a memory cell are normal, and indirectly checks whether or not a word line, a bit line and a peripheral circuit in a memory cell array are normal. That is, a trouble is not directly detected. Also, in a flash memory, a writing operation takes so much time as compared with a reading operation. In addition, in order to carry out an overwriting operation, an erasing operation whose time is longer than that of the writing operation is required. This causes a demerit that a test time for a flash memory is longer than that for a RAM such as a SRAM (static random access memory) and a DRAM (dynamic random access memory) in which a reading operation takes almost the same time as a wiring operation. In order to reduce the test time, a simple test method that does not require the reading from and writing to the memory cell is desired.
With regard to the test that does not require the reading from and writing to the memory cell, for example, Japanese patent publication number JP-A-Heisei 5-159600 (patent literature 1) discloses a test circuit of a semiconductor memory. This test circuit is provided with a semiconductor memory, a transistor column, a pre-charging means; a grounding means and a judging means. The semiconductor memory includes a memory cell array that includes at least a word line. The transistor column is composed of a plurality of transistors, which is connected in parallel between a power source side and a ground side respectively. In each of the plurality of transistors, a decoding output of the semiconductor memory is supplied to a gate through the word line. The pre-charging means pre-charges a drain side of the transistor column in accordance with a control signal. The grounding means grounds a source side of the transistor column in accordance with the control signal. The judging means judges a failure of the word line, in accordance with the potential of the drain side of the transistor column.
Specifically, the patent literature 1 describes as follows. In this testing circuit, the transistor (the transistor column) whose gate is connected to the word line is arranged on the side opposite to a row decoder with the word line between, and its transistor is used to directly monitor the voltage of the word line. Consequently, the test time of the word line is reduced as compared with the conventional method that indirectly judges whether or not the word line is good on the basis of the reading from and writing to the memory cell. Specifically, in accordance with the control signal, an input of an inverter connected to the drain side of the transistor column is pre-charged to a power source voltage level, and after that, one word line is selected. As for an output of the inverter, its output timing in the case that only one word line is normally selected is different from its output timing in the case that a failure causes the plurality of word lines to be multiply selected. Thus, by measuring its output timing by the judging means, it can be judged whether or not the word line is normal. Also, in a case of a failure in which the word line is not selected at all, the output of the inverter still remains at the ground level. Hence, it can be similarly judged whether or not the word line is good.
Also, with regard to the test that does not require the reading from and writing to the memory cell, Japanese patent publication number JP-P 2000-353399A (corresponding U.S. Pat. No. 6,111,801A: patent literature 2) discloses a method of testing a word line of a memory array and a related circuit. Here, the memory array has a plurality of memory cells arranged on a plurality of rows. Each of the plurality of rows has each of word lines connected to each of the plurality of memory cells. In order to activate at least one of the respective word lines in accordance with a corresponding address signal that is decoded by a decoding circuit, the related circuit has the decoding circuit that is connected to the word lines. The test method is characterized by having the respective steps of applying the address signal to the decoding circuit in order to activate the corresponding one of the respective word lines; and monitoring the corresponding one of the respective word lines in order to determine whether or not the corresponding one of the respective word lines is activated.
Specifically, this is described as follows. In this test method, a row test circuit is arranged in a memory cell array, and the row test circuit is used to monitor whether or not the word line is activated. Thus, although a complex test pattern is conventionally required and a long calculation time is required in order to execute the test, its cost is reduced. Further specifically, in the row test circuit, a latch block is arranged for each word line, and a state of activation=“1” or non-activation “0” of the word line is held therein. If the word line is normally selected, “1” is returned through a wired OR. Thus, it can be directly tested whether or not the “row” is normal. Hence, the test cost can be suppressed.
JP-A-Heisei 5-159600 and JP-P 2000-353399A describe the tests that do not require the reading from and writing to the memory cell. However, the present inventor has now discovered the following problems by the research.
JP-A-Heisei 5-159600 has a problem that it is difficult to design the test circuit. In this test circuit, a time until the input voltage of the inverter arrives at the ground level in the case when one word line is normally selected is different from that in the case when the abnormality causes the plurality of word lines to be selected. Thus, it is required to measure this time difference by the judging means. However, in order to obtain a merit that the test time is made short, the time for the potential change is required to be similar to or shorter than at least the time necessary for the reading from and writing to the memory cell. On the other hand, when no word line is selected, the input of the inverter implies the power source voltage. However, actually, there is the potential change caused by leakage. Thus, even if no word line is selected and if the measurement time is excessively long, the input of the inverter will arrives at the ground level in a short time. At the test under a high temperature, the time for the potential change caused by the leakage becomes shorter. Thus, it is considered that the judging means is required to be able to measure the timing at a precision in a range between several nanoseconds and several tens of nanoseconds. This implies that the timing precision similar to that for the timing design of the memory cell array is required even for the timing design of the testing circuit. That is, this has the problem that the design of the testing circuit is difficult.
Also, JP-P 2000-353399A has a problem that an area overhead of the row test circuit is large. This test method monitors the word line in order to judge whether or not the word line is selected. The method monitors the word line based on the judgment using a logical level. Thus, in order to carry out the method, a latch circuit (row test circuit) is required to be arranged for each word line. However, a plurality of transistors is required for each latch circuit. Thus, the area overhead becomes very large.
A simple test method that does not require reading from and writing to a memory cell is desired.